logic gate
英 [ˈlɒdʒɪk ɡeɪt]
美 [ˈlɑːdʒɪk ɡeɪt]
n. 逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
牛津词典
noun
- 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .
英英释义
noun
- a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
双语例句
- On the basis of operation rules of fuzzy number and of logic gate operator the probabilities of occurrence of middle events and top events were calculated, thus provided basis on enhancing the reliability design of system.
根据模糊数及逻辑门算子的运算规则，计算出了各中间事件及顶事件发生的概率，为提高系统的可靠性设计提供了依据。 - Based on the dual-rail logic, a cascadable parallel binary logic gate was, proposed.
基于双轨逻辑，本文提出一种可级联的并行二值逻辑门。 - And a computer inside actually assembles with many digital circuits, while digital circuits can be seen as the logic gate network that achieve by the electronic devices.
而一台电子计算机的内部实际上是由许许多多个数字电路组成，而数字电路可以看作是用电子器件实现的逻辑门网络。 - Implication Logic Function and Implication Logic Gate
蕴函逻辑函数和蕴函逻辑门的研究 - Reversible logic gate cascade is an important part of reversible logic synthesis.
可逆逻辑门级联是可逆逻辑综合的重要组成部分。 - Hermetically sealed, very high speed, logic gate optocoupler.
密封，非常高的速度，逻辑门光耦合器。 - Generally speaking, the video codec in portable system can be realized by two ways: Pure software way of DSP ( digital signal processor) and pure hardware way of ASIC or FPGA ( programmable logic gate array).
一般来说视频编解码器在便携式系统上的实现有以下两种方式：纯软件的DSP（数字信号处理）方式、纯硬件的ASIC（专用集成芯片）或者FPGA（可编程逻辑门阵列）。 - Based on the double parameter logic gate control, a new fuzzy control logic is presented and a two-stage fuzzy logic controller based on wheel angle acceleration is designed.
文中以双参数逻辑门限控制方法为基础提出了新的模糊控制逻辑，设计了基于车轮角加速度的两级模糊防抱控制器； - Use the quantum logic gate for implementing multi-purpose quantum cloning machine.
利用通用量子门实现多用途量子克隆机的方案。 - This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
本文介绍了一种新的数码乘法器结构：采用一级逻辑门结构实现阵列式数码乘法器，并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。